1. Field of the Invention
This invention relates to ring counter structures, and more particularly to ring counters having synchronously controlled counting flip-flops, the flip-flops each being constructed of a masterslave flip-flop with a majority decision input circuit for three variables. Two of these variables are applied to the set and reset inputs, while the third variable is obtained as the output of the slave. The majority decision circuit is directly connected to the set input of the master and indirectly to the reset input of the master by way of an inverter so that the counting flip-flop operates in accordance with the truth table
S R Qto Qtl ______________________________________ L O O O L L O L O L L L O O L O L O L L L L L L O L O O O O O O ______________________________________
which complies with the Boolean equation EQU Qt1 = S .sup.. R + Q to .sup.. (S + R).
2. description of the Prior Art
Usually, synchronously controlled ring counters comprise ring connected bistable storage circuits, for example flip-flops, only one of which is respectively marked. The synchronously operating ring counters differ from the asynchronously controlled counters in that all counting flip-flops are subjected to a common timing pulse. With this type of operation, the marked position is shifted by one position in the counting direction after a pulse arrives at the input of the ring counter. Such counting circuits have the advantage that a decoding circuit for indicating the respective counting result is not required since an indicator device can be directly connected to the outputs of the counting flip-flops.